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LH5116/H
FEATURES * 2,048 x 8 bit organization * Access time: 100 ns (MAX.) * Power consumption: Operating: 220 mW (MAX.) Standby: 5.5 W (MAX.) * Single +5 V power supply * Fully-static operation * TTL compatible I/O * Three-state outputs * Wide temperature range available LH5116H: -40 to +85C * Packages: 24-pin, 600-mil DIP 24-pin, 300-mil SK-DIP 24-pin, 450-mil SOP
CMOS 16K (2K x 8) Static RAM
DESCRIPTION
The LH5116/H are static RAMs organized as 2,048 x 8 bits. It is fabricated using silicon-gate CMOS process technology. It features high speed access in read mode using output enable (tOE).
PIN CONNECTIONS
24-PIN DIP 24-PIN SK-DIP 24-PIN SOP A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Vcc A8 A9 WE OE A10 CE I/O8 I/O7 I/O6 I/O5 I/O4
5116-1
Figure 1. Pin Connections for DIP, SK-DIP, and SOP Packages
1
LH5116/H
CMOS 16K (2K x 8) Static RAM
ROW DECODERS
ROW ADDRESS BUFFERS
A0 8 A5 3 A6 2 A7 1 A8 23 A9 22 A10 19 I/O1 9 I/O2 10 I/O3 11 I/O4 13 I/O5 14 I/O6 15 I/O7 16 I/O8 17
MEMORY CELL ARRAY (128 x128)
24 VCC 12 GND
CE
DATA CONTROL
COLUMN I/O CIRCUIT
COLUMN DECODERS
COLUMN ADDRESS BUFFERS CE
CE 18 WE 21 OE 20 4 A4 5 A3 6 A2 7 A1
5116-2
Figure 2. LH5116/H Block Diagram
PIN DESCRIPTION
SIGNAL PIN NAME SIGNAL PIN NAME
A0 - A10 CE OE WE
Address input Chip Enable input Output Enable input Write Enable input
I/O1 - I/O8 VCC GND
Data input/output Power supply Ground
TRUTH TABLE
CE OE WE MODE I/O1 - I/O8 SUPPLY CURRENT NOTE
L L H L
NOTE: 1. X = H or L
X L X H
L H X X
Write Read Deselect Outputs disable
DIN DOUT High-Z High-Z
Operating (ICC) Operating (ICC) Standby (ISB ) Operating (ICC)
1 1 1
2
CMOS 16K (2K x 8) Static RAM
LH5116/H
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT NOTE
Supply voltage Input voltage Operating temperature Storage temperature
VCC VIN Topr Tstg
-0.3 to +7.0 -0.3 to VCC + 0.3 0 to +70 -40 to +85 -55 to +150
V V C C
1 1 2 3
NOTES: 1. The maximum applicable voltage on any pin with respect to GND. 2. Applied to the LH5116/D/NA 3. Applied to the LH5116H/HD/HN
RECOMMENDED OPERATING CONDITIONS 1
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply voltage Input voltage
VCC VIH VIL
4.5 2.2 -0.3
5.0
5.5 VCC + 0.3 0.8
V V V
NOTE: 1. TA = 0 to 70C (LH5116/D/NA), TA = -40 to +85C (LH5116H/HD/HN)
DC CHARACTERISTICS 1 (VCC = 5 V 10%)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Output `LOW' voltage Output `HIGH' voltage Input leakage current Output leakage current Operating current Standby current
VOL VOH ILI ILO ICC1 ICC2 ISB
IOL = 2.1 mA IOH = -1.0 mA VIN = 0 V to VCC CE = VIH, VI/O = 0 V to VCC Outputs open (OE = VCC) Outputs open (OE = VIH) CE VCC - 0.2 V All other input pins = 0 V to VCC
0.4 2.4 -1.0 -1.0 25 30 1.0 1.0 30 40 1.0 0.2
V V A A mA mA A 2 3 4
NOTES: 1. TA = 0 to 70C (LH5116/D/NA), TA = -40 to +85C (LH5116H/HD/HN) 2. CE = 0 V; all other input pins = 0 V to VCC 3. CE = VIL; all other input pins = VIL to VIH 4. TA = 25C
AC CHARACTERISTICS 1 (1) READ CYCLE (VCC = 5 V 10%)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Read cycle time Address access time Chip enable access time Chip enable Low to output in Low-Z Output enable access time Output enable Low to output in Low-Z Chip disable to output in High-Z Output disable to output in High-Z Output hold time
tRC tAA tACE tCLZ tOE tOLZ tCHZ tOHZ tOH
100 100 100 10 40 10 0 0 10 40 40
ns ns ns ns ns ns ns ns ns
2 2 2 2
NOTES: 1. TA = 0 to 70C (LH5116/NA/D). TA = -40 to 85C (LH5116H/HD/HN). 2. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
3
LH5116/H
CMOS 16K (2K x 8) Static RAM
(2) WRITE CYCLE 1 (VCC = 5 V 10%)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTE
Write cycle time Chip enable to end of write Address valid time Address setup time Write pulse width Write recovery time Output active from end of write WE Low to output in High-Z Data valid to end of write Data hold time Output enable to output in High-Z Output active from end of write
tWC tCW tAW tAS tWP tWR tOW tWHZ tDW tDH tOHZ tOW
100 80 80 0 60 10 10 0 30 10 0 10 40 30
ns ns ns ns ns ns ns ns ns ns ns ns 2 2 2 2
NOTES: 1. TA = 0 to +70C (LH5116/D/NA), TA = -40 to +85C (LH5116H/HD/HN) 2. Active output to high-impedance and high-impedance to output active tests specified for a 200 mV transition from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER MODE NOTE
Input voltage amplitude Input rise/fall time Timing reference level Output load condition
NOTE: 1. Includes scope and jig capacitance.
0.8 V to 2.2 V 10 ns 1.5 V 1TTL + CL (100 pF) 1
DATA RETENTION CHARACTERISTICS 1
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Data retention voltage Data retention current Chip disable to data retention Recovery time
VCCDR ICCDR tCDR tR
CE VCCRC - 0.2 V CE VCCDR - 0.2 V, VCCDR = 2.0 V
2.0
5.5 1.0 0.2
V A ns ns 3 2
0 tRC
NOTES: 1. TA = 0 to +70C (LH5116/D/NA), TA = -40 to +85C (LH5116H/HD/HN) 2. TA = 25C 3. t RC = Read cycle time
CAPACITANCE 1 (f = 1 MHz, TA = 25C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT
Input capacitance Input/output capacitance
CIN CI/O
VIN = 0 V VI/O = 0 V
7 10
pF pF
NOTE: 1. This parameter is sampled and not production tested.
4
CMOS 16K (2K x 8) Static RAM
LH5116/H
tCDR VCC 4.5 V 2.2 V VCCDR CE 0V
DATA RETENTION MODE
tR
CE VCCDR -0.2 V
5116-6
Figure 3. Low Voltage Data Retention
tRC
A0 - A10 tAA tACE CE tOE OE tOLZ tCLZ DOUT NOTE: WE = "HIGH"
DATA VALID
tOH
tCHZ
tOHZ
5116-3
Figure 4. Read Cycle
5
LH5116/H
CMOS 16K (2K x 8) Static RAM
tWC A0 - A10 tAW tWR (NOTE 3)
tCW
CE tAS tWP (NOTE 2) WE tWHZ (NOTE 4) DOUT tDW tDH (NOTE 6) tOW (NOTE 5)
DIN NOTES: OE = 'LOW'
1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pin is in the output state. During this state, input signals of opposite logic level must not be applied.
5116-4
Figure 5. Write Cycle 1
tWC A0 - A10 tAW (NOTE 3) tWR
OE tCW CE tAS tWP (NOTE 2) WE tOHZ tOW (NOTE 5) DOUT (NOTE 4) tDW tDH (NOTE 6) DIN NOTES: 1. WE must be HIGH when there is a change in A0 - A10. 2. When CE and WE are both LOW at the same time, write occurs during the period tWP. 3. tWR is the time from the rise of CE or WE, whichever is first, to the end of the write cycle. 4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance. 5. DOUT outputs data with the same logic level as the input data of this write cycle. 6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input signals of opposite logic level must not be applied. tOLZ
5116-5
Figure 6. Write Cycle 2 6
CMOS 16K (2K x 8) Static RAM
LH5116/H
ACCESS TIME VS. SUPPLY VOLTAGE
ACCESS TIME tAA, tACE (RELATIVE VALUE) ACCESS TIME tAA, tACE (RELATIVE VALUE)
1.2
ACCESS TIME VS. AMBIENT TEMPERATURE 1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8 4.0
0.8 0 25 50 75 100 AMBIENT TEMPERATURE TA (C)
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE VCC (V)
AVERAGE SUPPLY CURRENT VS. SUPPLY VOLTAGE 25
AVERAGE SUPPLY CURRENT ICC (mA) AVERAGE SUPPLY CURRENT ICC (mA)
AVERAGE SUPPLY CURRENT VS. AMBIENT TEMPERATURE 25
20
20
15
15
10
10
5 4.0
5 4.5 5.0 5.5 6.0 0 25 50 75 100 SUPPLY VOLTAGE VCC (V) AMBIENT TEMPERATURE TA (C) INPUT VOLTAGE VS. AMBIENT TEMPERATURE
2.5
INPUT VOLTAGE VS. SUPPLY VOLTAGE
2.5
INPUT VOLTAGE VIH, VIL (V)
INPUT VOLTAGE VIH, VIL (V)
2.0
2.0
VIH 1.5 VIL 1.0
1.5 VIH 1.0 VIL
0.5 4.0
0.5 4.5 5.0 5.5 6.0 0 25 50 75 100 SUPPLY VOLTAGE VCC (V) AMBIENT TEMPERATURE TA (C)
5116-7
Figure 7. Electrical Characteristic Curves (VCC = 5 V, TA = 25C unless otherwise specified)
7
LH5116/H
CMOS 16K (2K x 8) Static RAM
PACKAGE DIAGRAMS
24DIP (DIP024-P-0600)
24 13
DETAIL
13.45 [0.530] 12.95 [0.510] 0 TO 15 0.30 [0.012] 0.20 [0.008] 1 31.30 [1.232] 30.70 [1.209] 4.45 [0.175] 4.05 [0.159] 5.30 [0.209] 4.90 [0.193] 3.45 [0.136] 3.05 [0.120] 0.51 [0.020] MIN 2.54 [0.100] TYP. 0.60 [0.024] 0.40 [0.016] MAXIMUM LIMIT MINIMUM LIMIT 15.24 [0.600] TYP. 12
DIMENSIONS IN MM [INCHES]
24DIP-2
24-pin, 600-mil DIP
24SDIP (SDIP024-P-0300)
24 13 6.55 [0.258] 6.15 [0.242] 1 22.25 [0.876] 21.75 [0.856] 3.65 [0.144] 3.25 [0.128] 4.40 [0.173] 4.00 [0.157] 3.45 [0.136] 3.05 [0.120] 1.778 [0.070] TYP. 0.51 [0.020] MIN 0.56 [0.022] 0.36 [0.014] 12 0.30 [0.012] 0.20 [0.008]
DETAIL
0 TO 15
7.62 [0.300] TYP.
DIMENSIONS IN MM [INCHES]
MAXIMUM LIMIT MINIMUM LIMIT
24SDIP
24-pin, 300-mil SK-DIP
8
CMOS 16K (2K x 8) Static RAM
LH5116/H
24SOP (SOP024-P-0450B)
1.27 [0.050] TYP. 1.70 [0.067] 13 8.80 [0.346] 12.40 [0.488] 8.40 [0.331] 11.60 [0.457]
0.50 [0.120] 0.30 [0.012]
24
10.60 [0.417]
1 15.60 [0.614] 15.20 [0.598]
12 1.70 [0.067] 0.20 [0.008] 0.10 [0.004] 0.15 [0.006] 1.025 [0.040] 2.40 [0.094] 2.00 [0.079] 0.20 [0.008] 0.00 [0.000] 1.025 [0.040] MAXIMUM LIMIT MINIMUM LIMIT
DIMENSIONS IN MM [INCHES]
24SOP
24-pin, 450-mil SOP
9
LH5116/H
CMOS 16K (2K x 8) Static RAM
ORDERING INFORMATION (TA = 0C to 70C)
LH5116 Device Type X Package - ## Speed 10 100 Access Time (ns)
Blank 24-pin, 600-mil DIP (DIP024-P-0600) D 24-pin, 300-mil SK-DIP (DIP024-P-0300) N 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM
Example: LH5116N-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP)
5116-8
ORDERING INFORMATION (TA = -40C to +85C)
LH5116H Device Type X Package - ## Speed 10 100 Access Time (ns) Blank 24-pin, 600-mil DIP (DIP024-P-0600) D 24-pin, 300-mil SK-DIP (DIP024-P-0300) N 24-pin, 450-mil SOP (SOP024-P-0450B) CMOS 16K (2K x 8) Static RAM Example: LH5116HN-10 (CMOS 16K (2K x 8) Static RAM, 100 ns, 24-pin, 450-mil SOP)
5116-9
10

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